View ATTINY11-6SU_873270.PDF datasheet online --- IC-ON-LINE

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Features
* Utilizes the AVR(R) RISC Architecture * AVR - High-performance and Low-power RISC Architecture
- 90 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General-purpose Working Registers - Up to 4 MIPS Throughput at 4 MHz Nonvolatile Program Memory - 2K Bytes of Flash Program Memory - Endurance: 1,000 Write/Erase Cycles - Programming Lock for Flash Program Data Security Peripheral Features - Interrupt and Wake-up on Low-level Input - One 8-bit Timer/Counter with Separate Prescaler - On-chip Analog Comparator - Programmable Watchdog Timer with On-chip Oscillator - Built-in High-current LED Driver with Programmable Modulation Special Microcontroller Features - Low-power Idle and Power-down Modes - External and Internal Interrupt Sources - Power-on Reset Circuit with Programmable Start-up Time - Internal Calibrated RC Oscillator Power Consumption at 1 MHz, 2V, 25C - Active: 3.0 mA - Idle Mode: 1.2 mA - Power-down Mode: <1 A I/O and Packages - 11 Programmable I/O Lines, 8 Input Lines and a High-current LED Driver - 28-lead PDIP, 32-lead TQFP, and 32-pad MLF Operating Voltages - VCC: 1.8V - 5.5V for the ATtiny28V - VCC: 2.7V - 5.5V for the ATtiny28L Speed Grades - 0 - 1.2 MHz for the ATtiny28V - 0 - 4 MHz For the ATtiny28L
*
*
*
8-bit Microcontroller with 2K Bytes of Flash ATtiny28L ATtiny28V Summary
*
* * *
Pin Configurations
PDIP TQFP/QFN/MLF
PD2 PD1 PD0 RESET PA0 PA1 PA3 PA2 (IR) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16
PD5 PD6 PD7 (AIN0) PB0 (AIN1) PB1 (T0) PB2 (INT0) PB3 (INT1) PB4
RESET PD0 PD1 PD2 PD3 PD4 VCC GND XTAL1 XTAL2 PD5 PD6 PD7 (AIN0) PB0
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
PA0 PA1 PA3 PA2 (IR) PB7 PB6 GND NC VCC PB5 PB4 (INT1) PB3 (INT0) PB2 (T0) PB1 (AIN1)
PD3 PD4 NC VCC GND NC XTAL1 XTAL2
1 2 3 4 5 6 7 8
PB7 PB6 NC GND NC NC VCC PB5
Rev. 1062FS-AVR-07/06
Note: This is a summary document. A complete document 1 is available on our Web site at www.atmel.com.
Description
The ATtiny28 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny28 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general-purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. Figure 1. The ATtiny28 Block Diagram
VCC 8-BIT DATA BUS INTERNAL OSCILLATOR GND PROGRAM COUNTER STACK POINTER WATCHDOG TIMER MCU CONTROL REGISTER TIMER/ COUNTER TIMING AND CONTROL RESET OSCILLATOR XTAL1 XTAL2 INTERNAL CALIBRATED OSCILLATOR
Block Diagram
PROGRAM FLASH INSTRUCTION REGISTER INSTRUCTION DECODER
HARDWARE STACK
GENERAL PURPOSE REGISTERS Z
INTERRUPT UNIT
CONTROL LINES
ALU
STATUS REGISTER HARDWARE MODULATOR PROGRAMMING LOGIC
ANALOG COMPARATOR
DATA REGISTER PORTB
DATA REGISTER PORTD
DATA DIR REG. PORTD
DATA REGISTER PORTA CONTROL PORTA REGISTER
+ -
PORTB
PORTD
PORTA
The ATtiny28 provides the following features: 2K bytes of Flash, 11 general-purpose I/O lines, 8 input lines, a high-current LED driver, 32 general-purpose working registers, an 8-bit timer/counter, internal and external interrupts, programmable Watchdog Timer with internal oscillator and 2 software-selectable power-saving modes. The Idle Mode stops the CPU while allowing the timer/counter and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. The wake-up or inter-
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ATtiny28L/V
rupt on low-level input feature enables the ATtiny28 to be highly responsive to external events, still featuring the lowest power consumption while in the power-down modes. The device is manufactured using Atmel's high-density, nonvolatile memory technology. By combining an enhanced RISC 8-bit CPU with Flash on a monolithic chip, the Atmel ATtiny28 is a powerful microcontroller that provides a highly flexible and cost-effective solution to many embedded control applications. The ATtiny28 AVR is supported with a full suite of program and system development tools including: macro assemblers, program debugger/simulators, in-circuit emulators and evaluation kits.
Pin Descriptions
VCC GND Port A (PA3..PA0) Supply voltage pin. Ground pin. Port A is a 4-bit I/O port. PA2 is output-only and can be used as a high-current LED driver. At VCC = 2.0V, the PA2 output buffer can sink 25 mA. PA3, PA1 and PA0 are bi-directional I/O pins with internal pull-ups (selected for each bit). The port pins are tristated when a reset condition becomes active, even if the clock is not running. Port B is an 8-bit input port with internal pull-ups (selected for all Port B pins). Port B pins that are externally pulled low will source current if the pull-ups are activated. Port B also serves the functions of various special features of the ATtiny28 as listed on page 27. If any of the special features are enabled, the pull-up(s) on the corresponding pin(s) is automatically disabled. The port pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D (PD7..PD0) Port D is an 8-bit I/O port. Port pins can provide internal pull-up resistors (selected for each bit). The port pins are tri-stated when a reset condition becomes active, even if the clock is not running. Input to the inverting oscillator amplifier and input to the internal clock operating circuit. Output from the inverting oscillator amplifier. Reset input. An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
Port B (PB7..PB0)
XTAL1 XTAL2 RESET
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Register Summary
Address
$3F $3E ... $20 $1F $1E $1D $1C $1B $1A $19 $18 $17 $16 $15 $14 $13 $12 $11 $10 $0F $0E $0D $0C $0B $0A $09 $08 $07 $06 $05 $04 $03 $02 $01 $00
Name
SREG Reserved Reserved Reserved Reserved Reserved Reserved Reserved PORTA PACR PINA Reserved Reserved PINB Reserved Reserved Reserved PORTD DDRD PIND Reserved Reserved Reserved Reserved Reserved Reserved Reserved ACSR MCUCS ICR IFR TCCR0 TCNT0 MODCR WDTCR OSCCAL
Bit 7
I
Bit 6
T
Bit 5
H
Bit 4
S
Bit 3
V
Bit 2
N
Bit 1
Z
Bit 0
C
Page
page 6
-
-
-
-
PORTA3 DDA3 PINA3
PORTA2 PA2HC -
PORTA1 DDA1 PINA1
PORTA0 DDA0 PINA0
page 32 page 32 page 32
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
page 32
PORTD7 DDD7 PIND7
PORTD6 DDD6 PIND6
PORTD5 DDD5 PIND5
PORTD4 DDD4 PIND4
PORTD3 DDD3 PIND3
PORTD2 DDD2 PIND2
PORTD1 DDD1 PIND1
PORTD0 DDD0 PIND0
page 33 page 33 page 33
ACD PLUPB INT1 INTF1 FOV0 ONTIM4 -
INT0 INTF0 ONTIM3 -
ACO SE LLIE ONTIM2 -
ACI SM TOIE0 TOV0 OOM01 ONTIM1 WDTOE
ACIE WDRF ISC11 OOM00 ONTIM0 WDE
ISC10 CS02 MCONF2 WDP2
ACIS1 EXTRF ISC01 CS01 MCONF1 WDP1
ACIS0 PORF ISC00 CS00 MCONF0 WDP0
page 44 page 19 page 22 page 23 page 35 page 36 page 43 page 37 page 9
Timer/Counter0 (8-bit)
Oscillator Calibration Register
Notes:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. Some of the status flags are cleared by writing a logical "1" to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.
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Instruction Set Summary
Mnemonic
ADD ADC SUB SUBI SBC SBCI AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER RJMP RCALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID Rd, Rr Rd, Rr Rd, Rr Rd, K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k
Operands
Rd, Rr Rd, Rr Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd, K Rd, K Rd Rd Rd Rd Rd k k
Description
Add Two Registers Add with Carry Two Registers Subtract Two Registers Subtract Constant from Register Subtract with Carry Two Registers Subtract with Carry Constant from Reg. Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Relative Jump Relative Subroutine Call Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less than Zero, Signed Branch if Half-carry Flag Set Branch if Half-carry Flag Cleared Branch if T-flag Set Branch if T-flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled
Operation
Rd Rd + Rr Rd Rd + Rr + C Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd $FF - Rd Rd $00 - Rd Rd Rd v K Rd Rd * (FFh - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd $FF PC PC + k + 1 PC PC + k + 1 PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b) = 0) PC PC + 2 or 3 if (Rr(b) = 1) PC PC + 2 or 3 if (P(b) = 0) PC PC + 2 or 3 if (P(b) = 1) PC PC + 2 or 3 if (SREG(s) = 1) then PC PC + k + 1 if (SREG(s) = 0) then PC PC + k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V = 0) then PC PC + k + 1 if (N V = 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if (I = 1) then PC PC + k + 1 if (I = 0) then PC PC + k + 1
Flags
Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None I None Z,N,V,C,H Z,N,V,C,H Z N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None
# Clocks
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 4 4 1/2 1 1 1 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2
ARITHMETIC AND LOGIC INSTRUCTIONS
BRANCH INSTRUCTIONS
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1062FS-AVR-07/06
Instruction Set Summary (Continued)
Mnemonic
LD ST MOV LDI IN OUT LPM BIT AND BIT-TEST INSTRUCTIONS SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH NOP SLEEP WDR P, b P, b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left through Carry Rotate Right through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit Load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Two's Complement Overflow Clear Two's Complement Overflow Set T in SREG Clear T in SREG Set Half-carry Flag in SREG Clear Half-carry Flag in SREG No Operation Sleep Watchdog Reset (see specific descr. for Sleep function) (see specific descr. for WDR/timer) I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0) C, Rd(n+1) Rd(n), C Rd(7) Rd(7) C, Rd(n) Rd(n+1), C Rd(0) Rd(n) Rd(n+1), n = 0..6 Rd(3..0) Rd(7..4), Rd(7..4) Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Operands
Rd, Z Z, Rr Rd, Rr Rd, K Rd, P P, Rr
Description
Load Register Indirect Store Register Indirect Move between Registers Load Immediate In Port Out Port Load Program Memory
Operation
Rd (Z) (Z) Rr Rd Rr Rd K Rd P P Rr R0 (Z)
Flags
None None None None None None None
# Clocks
2 2 1 1 1 1 3
DATA TRANSFER INSTRUCTIONS
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Ordering Information
Speed (MHz) Power Supply (Volts) Ordering Code ATtiny28L-4AC ATtiny28L-4PC ATtiny28L-4MC 4 2.7 - 5.5 ATtiny28L-4AI ATtiny28L-4AU(2) ATtiny28L-4PI ATtiny28L-4PU(2) ATtiny28L-4MI ATtiny28L-4MU(2) ATtiny28V-1AC ATtiny28V-1PC ATtiny28V-1MC 1.2 1.8 - 5.5 ATtiny28V-1AI ATtiny28V-1AU(2) ATtiny28V-1PI ATtiny28V-1PU(2) ATtiny28V-1MI ATtiny28V-1MU(2) Package(1) 32A 28P3 32M1-A 32A 32A 28P3 28P3 32M1-A 32M1-A 32A 28P3 32M1-A 32A 32A 28P3 28P3 32M1-A 32M1-A Operation Range Commercial (0C to 70C)
Industrial (-40C to 85C)
Commercial (0C to 70C)
Industrial (-40C to 85C)
Notes:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also Halide free and fully Green.
Package Type 32A 28P3 32M1-A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP) 28-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 32-pad, 5x5x1.0 body, Lead Pitch 0.50mm, Quad Flat No-lead/Micro Lead Frame Package (QFN/MLF)
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1062FS-AVR-07/06
Packaging Information
32A
PIN 1 B
PIN 1 IDENTIFIER
e
E1
E
D1 D C
0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 0.95 8.75 6.90 8.75 6.90 0.30 0.09 0.45 NOM - - 1.00 9.00 7.00 9.00 7.00 - - - 0.80 TYP MAX 1.20 0.15 1.05 9.25 7.10 9.25 7.10 0.45 0.20 0.75 Note 2 Note 2 NOTE
A2
A
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum.
E1 B C L e
10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 32A REV. B
R
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ATtiny28L/V
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ATtiny28L/V
28P3
D
PIN 1
E1
A
SEATING PLANE
L B1 e E B
B2
A1
(4 PLACES)
C eB
0 ~ 15
REF
SYMBOL A A1 D E E1 B
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.508 34.544 7.620 7.112 0.381 1.143 0.762 3.175 0.203 - NOM - - - - - - - - - - - MAX 4.5724 - 34.798 8.255 7.493 0.533 1.397 1.143 3.429 0.356 10.160 Note 1 Note 1 NOTE
Note:
1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
B1 B2 L C eB e
2.540 TYP
09/28/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 28P3 REV. B
R
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1062FS-AVR-07/06
32M1-A
D D1
1 2 3
0
Pin 1 ID E1 E
SIDE VIEW
TOP VIEW
A2
A3 A1
K
P D2
A
0.08 C
COMMON DIMENSIONS (Unit of Measure = mm) MIN 0.80 - - NOM 0.90 0.02 0.65 0.20 REF 0.18 4.90 4.70 2.95 4.90 4.70 2.95 0.23 5.00 4.75 3.10 5.00 4.75 3.10 0.50 BSC 0.30 - - 0.20 - 0.40 - - 0.50 0.60 o 12 - 0.30 5.10 4.80 3.25 5.10 4.80 3.25 MAX 1.00 0.05 1.00 NOTE
SYMBOL A
P
Pin #1 Notch (0.20 R)
1 2 3
A1 A2 A3 E2 b
K
D D1 D2 E
b
e
L
E1 E2 e L P
BOTTOM VIEW
0
Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. K
5/25/06 2325 Orchard Parkway San Jose, CA 95131 TITLE 32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, 3.10 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO. 32M1-A REV. E
R
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ATtiny28L/V
Errata
All revisions
No known errata.
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Datasheet Revision History
Rev - 01/06G
Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 1. Updated chapter layout. 2. Updated "Ordering Information" on page 7.
Rev - 01/06G
1. Updated description for "Port A" on page 25. 2. Added note 6 in "DC Characteristics" on page 54. 3. Updated "Ordering Information" on page 7. 4. Added "Errata" on page 11.
Rev - 03/05F
1. Updated "Electrical Characteristics" on page 54. 2. MLF-package alternative changed to "Quad Flat No-Lead/Micro Lead Frame Package QFN/MLF". 3. Updated "Ordering Information" on page 7.
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1062FS-AVR-07/06
Atmel Corporation
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1062FS-AVR-07/06

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